Marvell Technology @MarvellTech

One of AI's three big problems is power consumption, which is becoming a hard constraint in AI infrastructure. Data center power limits are tightening, and a significant portion of the energy modern AI systems consume is spent simply moving data between compute and memory. Marvell Photonic Fabric technology addresses that directly. By integrating optics closer to the XPU, the platform delivers up to 2x greater energy efficiency compared to copper, while also supporting up to 2x more compute within the same power and space footprint. The same platform extends scale-up clusters beyond a single rack, and enables pod-scale memory sharing across systems. Senior Director of Product Management Uday Poosarla details how it all works together: mrvl.co/4g8fq2P

Memory architecture is a technical challenge, but it is also a financial one. This clip puts the economics in clear terms. At the International Semiconductor Industry Group (ISIG) Executive Summit, Sandeep Bharathi makes the capital allocation case for memory pooling. When processors cannot access their full dedicated memory, the unused capacity is stranded, generating cost without generating value. Pooling that memory across systems can reduce total cost of ownership by 50 to 70%. The business model implications follow directly: lower TCO, faster time to first token, and higher throughput per millisecond translate to better margins for hyperscalers running inference at scale. See the video here: mrvl.co/4fRGRy3

A powerful week at COMPUTEX 2026. Marvell brought forward breakthrough innovation and a compelling vision for the evolution of AI infrastructure. The energy was electric and the momentum across the ecosystem is unmistakable. Learn more: mrvl.co/4dCO6s7

For the 13th year, Marvell employees laced up and ran together, spanning 36 sites across the globe. The Marvell Global 5K has become more than an annual event. It reflects something true about how this company operates: the work is demanding, the problems we solve are consequential, and we do it as one team, no matter the time zone. Building the semiconductor infrastructure that powers AI takes endurance, precision, and the kind of collaboration that only comes from a team that genuinely enjoys working together. The Global 5K is a reminder of all three. Congratulations to every runner, volunteer, and organizer who made this year's event possible across six continents.

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The tension between memory access and compute performance is not a new problem. What is new is the scale at which AI infrastructure has made it urgent. In this clip from the International Semiconductor Industry Group (ISIG) Executive Summit, Marvell President of the Data Center Group Sandeep Bharathi traces the memory hierarchy challenge from early CPU design through to modern AI inference, and explains why re-architecting memory at the system level has become a foundational requirement. He also introduces CXL as one of the key techniques for bringing memory closer to compute, using a return to his restaurant analogy to illustrate why consistency and accessibility are equally critical.

At #COMPUTEX2026, Marvell Chairman and CEO Matt Murphy shared our vision for the next era of AI infrastructure. After major waves of innovation in compute and memory, connectivity is emerging as the next bottleneck in scaling AI. As bandwidth demands push the industry beyond the limits of copper interconnects, optics will play an increasingly important role in enabling what comes next. Jensen Huang of @nvidia joined Matt on stage for an energizing conversation about the future of AI infrastructure and how the Marvell and NVIDIA partnership is helping shape what comes next. We were also honored to be joined by Dr. Tien Wu of ASE. For more than a decade, Marvell and ASE have worked together to advance some of the industry’s most important technology transitions, demonstrating the power of long-term partnership and ecosystem collaboration. The future of AI will be built together. Watch the keynote replay: mrvl.co/4dCO6s7

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Transformer architecture can be difficult to conceptualize. This clip makes it considerably more accessible. At the International Semiconductor Industry Group (ISIG) Executive Summit, Marvell President of the Data Center Group Sandeep Bharathi walks through how large language models process information using a restaurant analogy, from the moment an order is taken through to the kitchen, the prep work, and the pantry. The parallel to encoder/decoder stages, KV caches, and memory fetches is intuitive and clearly drawn. The analogy also surfaces a fundamental challenge: modern AI inference has become an energy-intensive data movement problem, and memory access sits at the center of it.

Join the livestream now, as Marvell Chairman and CEO Matt Murphy addresses the audience at @computextaipei: mrvl.co/4dCO6s7

What is the most powerful energy-efficient computer ever built? The answer has important implications for how the industry should think about AI infrastructure. In this clip from the International Semiconductor Industry Group (ISIG) Executive Summit, Marvell President of the Data Center Group Sandeep Bharathi opens with a deceptively simple question and draws a direct line from human biology to one of the most pressing design challenges in AI: the relationship between compute and memory.

COMPUTEX KICKS OFF TONIGHT! In the wee hours of the morning in North America, the Computex Taipei 2026 conference is set to kick off in Taiwan! Here's a schedule of the MASSIVE keynote speaker docket for the conference. Which of these speakers are you most excited to hear from? @tradertvlive $SPY $QQQ $QCOM $MRVL $NVDA $INTC $NXPI @qualcomm @MarvellTech @intel @nvidia @NXP @cristianoamon @LipBuTan1

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2 weeks ago

EARNINGS AND EVENTS FOR JUNE 1-5, 2026 A new month is upon us! Prepare for the first trading week of June with our @ttvresearch weekly calendar for June 1-5! Expect high-profile tech earnings and economic data in the back half of the week. @traderTVLIVE $SPY $QQQ $CRDO $HPE

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Marvell today introduced Teralynx T100, the industry’s first 102.4 Tbps switch silicon purpose-built for the AI era. Unlike legacy switching platforms designed for traditional enterprise and cloud data centers, the Teralynx T100 was architected from the ground up for AI—enabling the industry’s lowest power consumption and lowest latency at this bandwidth tier to address critical bottlenecks in today’s large AI clusters. The T100 will start sampling to customers beginning this quarter. Learn more: mrvl.co/3Qe0WE7

The @computextaipei keynote by Marvell Chairman and CEO Matt Murphy is just one day away. His presentation, entitled “The Future of AI Scaling Depends on Connectivity,” will be livestreamed on the Marvell website. Learn more about the keynote and watch it here: mrvl.co/4dCO6s7

Co-packaged connectivity is scaling rapidly. Fewer than one million near- and co-packaged ports shipped in 2025; that figure is projected to surpass 100 million per year by 2030. Deploying technology at that volume requires standards that ensure interoperability, predictability and flexibility. The Open CPX MSA, a consortium that includes Marvell, is developing specifications for integrating NPO and CPO technology into switches and servers in scalable, repeatable ways, with support for co-packaged copper as well. Associate Vice President of Cloud Switch Marketing George Hervey outlines how the standard works, what it means for data center deployment, and why modular, interoperable frameworks are essential to meeting the pace of AI infrastructure buildout. Learn more: mrvl.co/4uD9TWn

The next phase of AI scaling will require new approaches to connectivity. As the end-to-end connectivity leader, Marvell enables the critical connections in modern AI infrastructure to maximize data movement, from within servers and racks to the networks linking data centers across regions, allowing hyperscalers and cloud providers to deploy AI-optimized systems with unprecedented performance, scale and efficiency. Chairman and CEO of Marvell, Matt Murphy, will deliver a keynote on this topic at @computextaipei, entitled “The Future of AI Scaling Depends on Connectivity.” The keynote will also be livestreamed on the Marvell website: mrvl.co/4dCO6s7

Copper continues to deliver in dense AI computing environments, and a recent demonstration at OFC 2026 shows how far the technology has advanced. Marvell and Luxshare-Tech demonstrated 224G long-range SerDes driving signals across a 2.5-meter CPC-backplane-CPC channel, achieving lane bit error rates of 1e-11 at 4 picojoules per bit. Up to 512 lanes of the technology could be integrated into a 102.4T switch. SerDes is the foundational building block of high-speed networking, with direct impact on power consumption, latency, bandwidth and total cost of ownership. Lowering power by a single picojoule per bit on a 200G/lane device can reduce system power consumption by up to 100 watts. Senior Staff Engineer Aatreya Chakravarti details the demonstration and the broader role SerDes plays in scaling AI data center infrastructure: mrvl.co/3PP6Tar

PCIe is the world's most widely deployed chip-to-chip interconnect, and its role in AI scale-up networks is growing. Low latency and high bandwidth make it well suited for the large, multi-rack clusters at the foundation of modern AI data centers. Marvell has demonstrated the industry's first 260-lane PCIe 6.0 switch, with 256 lanes of data traffic representing the highest radix available for a PCIe switch. The Marvell Structera S flattens the network topology, eliminating the need for multiple smaller switches and reducing complexity, latency and cost at scale. Krishna Mallampati and Joe Slember detail the technology and how it fits within the broader Marvell PCIe portfolio: mrvl.co/3RpxSKd

Marvell Chairman and CEO Matt Murphy will deliver a keynote at COMPUTEX on June 2, entitled “The Future of AI Scaling Depends on Connectivity.” The keynote will also be livestreamed on the Marvell website. In his address, Murphy will discuss the company’s decade-long investment in connectivity and optical technologies, and how Marvell has built the technology, product portfolio and ecosystem partnerships needed to help advance the future of AI infrastructure. Learn more about the keynote here: mrvl.co/3S38x8U

Energy efficiency is becoming a defining constraint in AI infrastructure, for both operating costs and data center power limits. At the same time, scale-up clusters are growing beyond single racks and memory subsystems are struggling to keep pace with workload demands. Marvell Photonic Fabric technology addresses all three challenges through optical interconnect and system-level design, delivering up to 2x greater energy efficiency compared to copper, sub-200ns XPU-to-XPU latency across distances up to 50 meters, and pod-scale memory sharing across racks. Senior Director of Product Management Uday Poosarla details the technology and its role within the broader Marvell connectivity portfolio: mrvl.co/4u2slrg

As optics migrate from front-panel modules to near-packaged and co-packaged configurations directly alongside compute die, the manufacturing challenge shifts as well. Testing methods designed for low-volume, custom configurations cannot scale to meet the demands of AI infrastructure production. In a new article, Senior Director of Product and Test Engineering Andrew Yick makes the case for treating optical test as a first-class manufacturing discipline, applying the same shift-left, design-for-test, and ATE-enabled approaches that have governed high-volume semiconductor production for decades. The core principle: if it cannot be tested like an integrated circuit, it will not scale like one. Learn more: mrvl.co/4nzfWsk

At OFC 2026, Marvell and Luxshare-Tech demonstrated the industry's first hybrid AEC/ACC cable, a new category of data center interconnect designed to optimize in-rack copper connectivity for AI infrastructure. Active electrical cables deliver longer reach; active copper cables offer lower power, latency and cost for shorter runs. The hybrid combines both, achieving 2.5 meters of reach at lower power than a standard AEC, without compromising data integrity. As the only provider delivering both ACC and AEC silicon solutions at 200G/lane, Marvell is positioned to support the full range of in-rack connectivity requirements as AI infrastructure continues to scale. Senior Principal Engineer Nicola Bramante details the technology and what it means for data center design flexibility. Learn more on the Marvell blog: mrvl.co/3Rcd9JE