Benjamin Rosseaux @coder
Programming for food, indie game programmer, hobby musician, demoscener under the handle BeRo in the demogroup Farbrausch. Want-Handle-Buyers GO AWAY! rosseaux.net Bingen am Rhein, Germany Joined February 2007-
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vkcube running on 64-bit RISC-V Alpine Linux in my PasRISCV Emulator with the Vulkan-based PasRISCVEmu UI backend. #riscv #vulkan @risc_v @VulkanAPI
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Guest Software rendered OpenGL kmscube running on a guest 64-bit RISCV Alpine Linux system in my PasRISCV emulator with active x86-64 Tracing JIT Dynarec compiler with smooth >= 60FPS 🙂 #RISCV #Emulation #JIT
but it is primarily targeted at embedded and low-power applications rather than high-performance computing. (5/5)
extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, (4/5)
The irony: the entire #RISCV base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, (1/5)
@TechByTaraa ... A far underrated language in my opinion, since the most knows only the old "School" Pascal with its bad reputation, and not the today modern Object Pascal.
@TechByTaraa Object Pascal, it's low-level like C and C++, it has inline-assembler, it is readable, it has a good standard library, it has modern features like RTTI, generics, anonymous functions and so on, it has good IDEs (Delphi and Lazarus), and it has a good community. ...
consistent design for more traditional SIMD instructions in the future, while still keeping the benefits of RVV for more advanced use cases. (3/3)
but it also makes it more complex and harder to implement a JIT compiler for it in my PasRISCV emulator, where the JIted code needs often to bailout to the interpreter for non-native-SIMDizable code cases. I hope that the RISC-V foundation can come up with a more clean and (2/3)
A small rant about vector extensions in RISC-V, although I like RISC-V in general. But why is RISC-V's vector extension (RVV) so different from other SIMD instruction sets like x86's SSE/AVX or ARM's NEON? It seems like RVV is designed to be more flexible and scalable, (1/3)
XOrg is also running in my PasRISCV emulator now. 🙂
@justbyte_ MS-DOS edit.com and the integrated editors of PowerBASIC 3.2 and Turbo Pascal 6
@TechByTaraa x86-16/x86-32/x86-64 Assembler (Intel Syntax, not AT&T Syntax), C, C++, C#, Object Pascal, POCA, PHP, Python, Java, JavaScript, TypeScript, PowerBASIC, QBasic, and some more
@akramcodez 3 years but with a 5 year old CPU (Ryzen 9 5950X), 64GB RAM, and a RTX4090. It's fast enough, and I don't feel the need to upgrade yet, especially in these days when hardware prices like RAM are quite high. I've also the near same setup with a AMD Raedon RX 9700 XT for tests.
@RinoTheBouncer On no console, on an Amstrad CPC6128 home computer, followed by x86 PCs.
PasRISCV's network device emulation is finally working 🙂
PasRISCV now has its own local CLI debugger alongside the GDB remote server. It supports breakpoints single-stepping register & memory inspection & allows simultaneous local CLI & remote GDB sessions. A public debugger API enables future GFX debugger UI. youtu.be/yznijHMKj_0
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